Master's Thesis - Oliver Gerler

rockus.at / gerler / mastersthesis /

 

Run-Time Task Reconfiguration on Multi Digital Signal Processor Systems

In this Master's thesis a run-time reconfiguration mechanism for multi-DSP systems with point-to-point communication has been developed to improve testability and maintainability. This mechanism is an extension of the rapid prototyping system PEPSY which allows the development of data-flow driven real-time applications. First, existing rapid prototyping systems, data-flow models and multi-DSP operating systems are investigated and compared. Principles of fault tolerance, test and reconfiguration are outlined. Second, an overview of PEPSY is given and the basic functions of the run-time reconfiguration mechanism are discussed. Subsequently, implementational details of the mechanism and the data transfer protocol between the host and the multi-DSP system are shown. Finally, in an experimental evaluation the quality and temporal behavior of the implementation are investigated.
PostScriptthesis.ps (963 KB)
DeVice Independentthesis.dvi (198 KB)
Portable Document Formatthesis.pdf (677 KB)
LaTeX sourcesthesis.tar.gz (1.3 MB)
LHArcthesis.lha (1.4 MB)
DSP kernel sourcekernoel.asm (23 KB)